Editing PS3

Noisebridge wants a cluster of PS3 systems running Linux.  See mailing list discussion [https://www.noisebridge.net/pipermail/noisebridge-discuss/2009-June/005626.html here].

I dropped off a PS3 Sunday, but ran out of time to finish configuring it.  I left it with Miloh and Jason D, but I don't know if they finished the install.  [[User:Dr jesus|Dr jesus]] 16:39, 22 June 2009 (PDT)

The other PS3 is up, hippo.noise.  Same configuration as goat.  [[User:Dr jesus|Dr jesus]] 13:10, 28 June 2009 (PDT)

''I (too) have a 60 GB PS3 I'd be willing to donate. Was hoping to sell it, but maybe one of you fine coders would help me with a python project and/or iPhone app I'm working on...  Regardless, I'll bring it by either this afternoon (June 18) or Tuesday (June 22).'' --[[User:Nthmost|Nthmost]] 23:23, 18 June 2009 (PDT)

== Tools ==

You really want to use llvm-gcc with the cellspu backend.  Gcc kind of sucks.  You also want to cross-compile from pony, since the hyperthreaded PowerPC in the PS3 is kind of slow.  There is a distcc service available on the French GCC cluster if pony doesn't cut it.  Talk to [[User:Dr jesus|Dr. Jesus]] for details.

Note that programming for the Cell requires making several significant architectural changes to any existing code base:

# Programming the CBE is all the fun of concurrent programming combined with all the joy of paged memory.
# The cell SPUs only have 256KiB of memory available.  However, it's SRAM and it's bolted directly onto the logic.  Pretend it's a big glob of L1 cache and you're talking to a SSE or Altivec unit, but the L1 cache has had a Haste spell cast on it, is late for a meeting, and is on fire.  For many of the SIMD instructions, ''the load/store latency is close to the instruction latency.''  
# The SPUs have to share that space (the "local store") for instructions and data.  
# Ha ha no branch prediction.  Unrolling, conditional load/store, and fucking with the linker is the norm.
# But you do get a prefetcher.  Cache lines are 128 bits, instructions are 32 bits, do the math.
# The SPEs like to eat in 128-bit chunks from their local store.  This means you want to feed it packed data if your data is not in 128-bit quantities.  
# But you do get intrinsics to swizzle and shuffle the data.
# However, the intrinsics follow the Altivec model.
# But you do have prefetcher hint intrinsics.
# However, the intrinsics contain potassium benzoate.
# A dedicated DMA core is available to page things in and out of each SPU.  See the IBM SDK.
# Inter-SPU communication is possible via a hardware mechanism, but might not be a good idea depending on how much data is being pushed.
# Immediates are 18 bits.  
# Yeah, about those floating point and integer division instructions... no.  Sorry about the SPARC flashback.
# You probably think those channel I/O intrinsics look like a good idea, but unless you've been spending a disturbing amount of time with the cycle accurate simulator you're probably wrong.

== Applications ==
* http://code.google.com/p/hashclash/
* https://documents.epfl.ch/users/l/le/lenstra/public/papers/lat.pdf   
* http://eprint.iacr.org/2009/259

== Donations ==
It looks like we need about $300 to make one happen (PS3 40GB on ebay). We can get more than one though, the more the merrier.

[[User:adi|adi]] is organizing donations.  Please add yourself to this list if you'd like to contribute.  Cash, check, or paypal accepted.
* [[User:adi|adi]] - $50
* [https://www.noisebridge.net/pipermail/noisebridge-discuss/2009-June/005627.html Josh] - $50
* David Molnar - $100
* [[User:charliep|Charlie]] - $100 (and no not thinking about playing games with it either)
* dpc - $75 (just to be different)
* [[User:Ioerror|Jacob]] - $50