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You really want to use llvm-gcc with the cellspu backend.  Gcc kind of sucks.  You also want to cross-compile from pony, since the hyperthreaded PowerPC in the PS3 is kind of slow.  There is a distcc service available on the French GCC cluster if pony doesn't cut it.  Talk to [[User:Dr jesus|Dr. Jesus]] for details.
You really want to use llvm-gcc with the cellspu backend.  Gcc kind of sucks.  You also want to cross-compile from pony, since the hyperthreaded PowerPC in the PS3 is kind of slow.  There is a distcc service available on the French GCC cluster if pony doesn't cut it.  Talk to [[User:Dr jesus|Dr. Jesus]] for details.


Note that programming for the Cell requires making several significant architectural changes to any existing code base:
Note that programming for the Cell requires making two significant architectural changes to any existing code base:


# Programming the CBE is all the fun of concurrent programming combined with all the joy of paged memory.
# The cell SPUs only have 256KiB of memory available.  However, it's SRAM and it's bolted directly onto the logic.  Pretend it's a big glob of L1 cache and you're talking to a SSE or Altivec unit, but the L1 cache has had a Haste spell cast on it, is late for a meeting, and is on fire.  For many of the SIMD instructions, ''the load/store latency is close to the instruction latency.''   
# The cell SPUs only have 256KiB of memory available.  However, it's SRAM and it's bolted directly onto the logic.  Pretend it's a big glob of L1 cache and you're talking to a SSE or Altivec unit, but the L1 cache has had a Haste spell cast on it, is late for a meeting, and is on fire.  For many of the SIMD instructions, ''the load/store latency is close to the instruction latency.''   
# The SPUs have to share that space (the "local store") for instructions and data.   
# The SPUs have to share that space (the "local store") for instructions and data.   
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# Yeah, about those floating point and integer division instructions... no.  Sorry about the SPARC flashback.
# Yeah, about those floating point and integer division instructions... no.  Sorry about the SPARC flashback.
# You probably think those channel I/O intrinsics look like a good idea, but unless you've been spending a disturbing amount of time with the cycle accurate simulator you're probably wrong.
# You probably think those channel I/O intrinsics look like a good idea, but unless you've been spending a disturbing amount of time with the cycle accurate simulator you're probably wrong.


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